Power field-effect transistors primarily include two different types, namely, vertical double-diffused MOSFET (VDMOS) and lateral double-diffused MOSFET (LDMOS). Compared to the VDMOS, LDMOS demonstrates a number of advantages. For example, the latter has better thermal stability and frequency stability, better gain and durability, lower feedback capacitance and thermal resistance, as well as a constant input impedance and a simpler bias circuit.
FIG. 1 shows a conventional N-type LDMOS device structure. The N-type LDMOS device structure includes a semiconductor substrate (not shown), a P-type well 100 formed in the semiconductor substrate, an N-type drift region 101 formed in the P-type well 100, a shallow trench isolation structure 104 formed in the N-type drift region 101. The shallow trench isolation structure 104 is used to increase the conduction path in the LDMOS device, to thus further increase the breakdown voltage of the device.
The N-type LDMOS device structure shown in FIG. 1 further includes a P-type body region 106 formed inside of the P-type well 100 on the side of the N-type drift region 101. A gate structure 105 is formed on the surface of the semiconductor substrate. The gate structure 105 is formed to across the P-type body region 106 and the N-type drift region 101 with a portion of the gate structure 105 located on the top of the shallow trench isolation structure 104. The gate structure 105 further includes a gate dielectric layer formed on the semiconductor substrate, a gate electrode formed on the top of the gate dielectric layer, and sidewalls formed on both sides of the gate dielectric layer and the gate electrode layer. A source region 102 is formed in the P-type body region 106 on one side of the gate structure 105 and a drain region 103 is formed in the N-type of drift area 101 on the other side of the gate structure 105. Both the source region 102 and the drain region 103 are doped with N-type dopant.
However, conventionally-fabricated LDMOS devices still have a very large size, which prevents further improvement of the degree of integration. The disclosed fabrication method and device structure are directed to decreasing the size of the LDMOS devices to solve one or more problems set forth above and other problems in the art.